? semiconductor components industries, llc, 2001 august, 2001 rev. 9 1 publication order number: cs1088/d cs1088 vacuum fluorescent display tube driver the vfd driver is a microprocessor interface ic that drives a multiplexed vf (vacuum fluorescent) display tube. it consists of a 34bit shift register, a 34bit transparent data latch, a metal mask rom, six 20 ma anode output drivers, twentyfive 2 ma anode output drivers, and three 50 ma grid drivers with output enables. features ? power on reset ? display dimming possible ? three, 50 ma grid drivers ? anodes: 6 @ 20 ma 25 @ 2 ma grid1grid2 grid3 gnd filament vfd port port port gnd v cc port v ign gnd 5 v 12 v m p regulator v bat clock chip select spi functions anodes gren stb clk d in cs1088 grid3 grid2 grid1 0.1 m f v bb gnd 1:31 figure 1. application diagram http://onsemi.com dip40 wide body n suffix case 711 device package shipping ordering information* dip40 wide body 9 units/rail CS1088XN40 see general marking information in the device marking section on page 7 of this data sheet. device marking information 40 1 *for additional package options, consult your local on semiconductor sales office.
cs1088 http://onsemi.com 2 maximum ratings* parameter value unit supply voltage (v bb ) 0.6 to +18 v input voltages (d in , clk, stb, gren) 0.6 to +6.0 v junction temperature range 40 to +150 c storage temperature range 55 to +150 c esd susceptibility (human body model) 2.0 kv esd susceptibility (machine model) 200 v package thermal resistance, dip40 junctiontocase, r q jc junctiontoambient, r q ja 20 45 c/w c/w lead temperature soldering: wave solder (through hole styles only) note 1 reflow (smd styles only) note 2 260 peak 230 peak c 1. 10 second maximum. 2. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. electrical characteristics (8.0 v v bb 16.5 v, gnd = 0 v, 40 c t j 105 c; unless otherwise stated. note 3.) parameter test conditions min typ max unit v bb input v bb input voltage 8.0 16.5 v i bb0 current no outputs active, v bb = 16.5 v 2.0 5.0 ma reset mode all outputs forced low. 6.5 7.5 v d in , clk, stb inputs v il1 , input low voltage 1.6 v v ih , input high voltage 3.3 v i il , input current v in = v ih 7.5 20.0 m a gren input v il , input low voltage 1.6 v v ih , input high voltage 3.3 v i ih , input pulldown current v in = 3.325 v 30 60 m a grid1, grid2, grid3 outputs i ol sink current 1.0 ma i oh source current 50 ma v ol i out = 1.0 ma 0.5 v v oh i out = 50 ma, v bb = 12 v v bb 0.75 v bb v an24 an29 outputs i ol sink current 400 m a i oh source current 20 ma v ol i out = 400 m a 0.5 v v oh i out = 20 ma, v bb = 12 v v bb 0.5 v bb v 3. designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production.
cs1088 http://onsemi.com 3 electrical characteristics (continued) (8.0 v v bb 16.5 v, gnd = 0 v, 40 c t j 105 c; unless otherwise stated. note 4.) parameter test conditions min typ max unit an1 an23 outputs i ol sink current 100 m a i oh source current 2.0 ma v ol i out = 100 m a 0.5 v v oh i out = 2.0 ma, v bb = 12 v v bb 0.5 v bb v ac characteristics: input and output timing f c , clk frequency 0 1.0 mhz t cl , clk low time 200 ns t ch , clk high time 200 ns t cr , clk rise time 100 ns t cf , clk fall time 100 ns t sc , stb low to clk high time 50 ns t st , stb high time 500 ns t an , stb high to anode output propagation delay 5.0 m s t gl , grid turn on propagation delay v bb = 12 v 2.0 m s t g0 , grid turn off propagation delay v bb = 12 v 5.0 m s t gr , grid rise time at rated load. note 5 0.50 2.00 m s t gf , grid fall time at rated load. note 5 0.35 2.00 m s t ar , anode rise time at rated load. note 5 0.40 2.00 m s t af , anode fall time at rated load. note 5 0.40 2.50 m s 4. designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production. 5. grid and anode rise / fall times are measured from 10% and 90% points. output currents are at the maximum rated currents for the respective stages.
cs1088 http://onsemi.com 4 package lead description package lead number lead symbol 40l dip (31 anode configuration) function 1 grid1 50 ma grid output. 2 grid2 50 ma grid output. 3 grid3 50 ma grid output. 4 an1 2.0 ma anode output. 5 an2 2.0 ma anode output. 6 an3 2.0 ma anode output. 7 an4 2.0 ma anode output. 8 an5 2.0 ma anode output. 9 an6 2.0 ma anode output. 10 an7 2.0 ma anode output. 11 an8 2.0 ma anode output. 12 an9 2.0 ma anode output. 13 an10 2.0 ma anode output. 14 an11 2.0 ma anode output. 15 an12 2.0 ma anode output. 16 an13 2.0 ma anode output. 17 an14 2.0 ma anode output. 18 an15 2.0 ma anode output. 19 an16 2.0 ma anode output. 20 gnd ground connection. 21 an17 2.0 ma anode output. 22 an18 2.0 ma anode output. 23 an19 2.0 ma anode output. 24 an20 2.0 ma anode output. 25 an21 2.0 ma anode output. 26 an22 2.0 ma anode output. 27 an23 2.0 ma anode output. 28 an24 20 ma anode output. 29 an25 20 ma anode output. 30 an26 20 ma anode output. 31 an27 20 ma anode output. 32 an28 20 ma anode output. 33 an29 20 ma anode output. 34 an30 2.0 ma anode output. 35 d in shift register data input. 36 clk shift register clock input. 37 stb transfer contents of shift registers to output stages. 38 gren grid outputs enable. 39 an31 2.0 ma anode output. 40 v bb supply voltage input.
cs1088 http://onsemi.com 5 an1 an23, an30, an31: 2.0 ma v reg por grid1 grid2 grid3 an1 an2 an3 an25 an26 an27 an28 an29 an30 an31 v bb gnd gren stb d in clk metal mask rom output drive capability grid outputs: 50 ma an24 an29: 20 ma dq le dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq clk r dq le dq le dq le dq le dq le dq le dq le dq le dq le dq le dq le dq le v reg v reg v reg v reg v reg figure 2. block diagram operation description upon the initial application of power, the power on reset function will cause all of the anode and grid driver outputs to be off and all shift register outputs to be set low. data is fed into the shift register through the d in pin at the rising edge of the clk input. thirty four bits of data are capable of being stored by the shift register. once the desired pattern is stored in the shift register, it can be transferred to the latch by setting the stb input high. the output of each latch drives its corresponding output stage. a logic high input to the shift register/latch will cause the corresponding output to turn on. a logic low input to the shift register/latch will cause the corresponding output to turn off. please note that if the stb is held high, the outputs of the latch reflect the outputs of the corresponding shift register bits and will change if data is shifted in. the three grid outputs are gated by the gren input. when gren is low, the grid outputs are forced low regardless of the state of the corresponding latch output. when gren is high, the grid outputs correspond to the state of their respective latch outputs. the anode outputs, an1 to an31 are always enabled.
cs1088 http://onsemi.com 6 application information table 1. bit pattern, g = grid, a = anode. bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 pin name g1 g2 g3 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 bit # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 pin name a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 2 34 56 78 9 32 33 34 12 3 1 clk in bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 32 bit 33 bit 34 bit 1 bit 2 bit 3 d in stb anodes gren grids * * selected grid goes high only if input bit pattern from shift register to grid is high. figure 3. typical operation unused grid and anode drivers should have their respective bits set to logic low in the data stream. multiple grid or anode drivers may be connected together, but must be programmed to the same logic state for proper device operation. maximum package power must be observed and care must be taken to maintian junction temperature below +150 c.
cs1088 http://onsemi.com 7 pin connections marking diagrams dip40 wide body n suffix case 711 40 1 cs1088 awlyyww 40 1 an17 gnd an18 an16 an19 an15 an20 an14 an21 an13 an22 an12 an23 an11 an24 an10 an25 an9 an26 an8 an27 an7 an28 an6 an29 an5 an30 an4 d in an3 clk an2 stb an1 gren grid3 an31 grid2 v bb grid1 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week
cs1088 http://onsemi.com 8 package dimensions notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 120 40 21 b a c seating plane d f g h k n m j l dim min max min max inches millimeters a 51.69 52.45 2.035 2.065 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040 dip40 wide body n suffix case 71103 issue c on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs1088/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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